library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity frq_gen is
    Port ( clk : in std_logic;
           set_d : in std_logic_vector(7 downto 0);
           ck_out : out std_logic);
end frq_gen;

architecture Behavioral of frq_gen is

signal sx    : std_logic_vector(8 downto 0);
signal s_bf  : std_logic_vector(7 downto 0);
signal o_count : std_logic_vector(7 downto 0);   

begin

process(clk,set_d) begin
	if clk='1' and clk'event then
		sx <= ( '0' & set_d) +('0' & s_bf);
	end if ;
end process;

process(clk) begin
	if clk='0' and clk'event then
      s_bf <= sx(7 downto 0);
	end if ;
end process;

process(sx(8)) begin
if sx(8)='1' and sx(8)'event then
   o_count <= o_count + 1 ;
end if ;
end process ;
   ck_out <= o_count(7) ;

end Behavioral;